Design Data & IP Release Management
Perforce P4 at chip scale (commit and edge servers, streams, file locking, large binaries), IP lifecycle tools, hierarchical IP versions and the bill of IP, IP release gates and deliverables, third-party IP intake, workspace disk, and branching for chip derivatives.
Overview
The job
A modern SoC at AMD, NVIDIA, Apple or Qualcomm is assembled from a few hundred IP blocks: CPU clusters, memory controllers, SerDes PHYs, standard-cell and memory libraries, analog macros, interconnect. Some are written in-house, some are licensed, and each is released many times before tape-out. The design data platform must answer two questions at any moment:
- Which exact version of every block is inside this chip? That is the bill of IP: a resolved, locked tree of IP versions.
- Is each of those versions good enough to use? That is the IP release gate: checks and deliverables recorded against an immutable release.
Build and release, CAD infrastructure and platform engineers own that platform: the version control servers (usually Perforce P4) spread over several design sites and a CI farm, the IP lifecycle layer on top, intake of vendor IP, and petabytes of workspaces. The tape-out checklist that consumes it is in Tape-out Release Engineering, and the CI tiers that produce the check results in The Chip Design Flow as a CI Pipeline (chip-design-flow-ci).
Interview questions
- Design the Perforce P4 deployment for 1,500 chip engineers at three sites plus a CI farm that runs 40,000 jobs a night.
- Model hierarchical IP and resolve the bill of IP for a chip. Two blocks require different versions of the same library. What happens?
- What does an IP release gate check before other teams may consume a new version of a hard macro?
- How do you take in third-party IP from a vendor and keep every chip that uses it current with fixes and errata?
- Workspaces on the project file system have grown to 2 PB and the filer is at 92 percent. How do you get it under control without stopping design work?
- A derivative chip shares 80 percent of its IP with the chip now in production. How do you branch so fixes flow to both without copying everything?
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