Emulation & FPGA Prototyping Pipelines
Simulation, emulation and FPGA prototyping as three speed and visibility tiers: emulator capacity as a booked resource, compile flows and their runtimes, firmware and OS boot before silicon, waveform data sizes and how it all plugs into CI.
Overview
Why this topic
RTL simulation sees every signal on every cycle, but a full system-on-chip runs at a few hundred cycles per second in it. Booting Linux takes billions of cycles, so in simulation it would take months. Software teams cannot wait for silicon to start on firmware, drivers and the OS, and verification teams need far more cycles than simulation can give.
Two kinds of hardware close that gap. An emulator (Cadence Palladium Z3, Synopsys ZeBu-200 and ZeBu Server 5, Siemens Veloce Strato CS) maps the design onto custom processors or FPGAs and runs it around a megahertz with good debug visibility. An FPGA prototype (Synopsys HAPS-200, Cadence Protium X3, Siemens Veloce Primo CS and proFPGA CS) runs it at tens of megahertz with far less visibility. A full-size system costs millions of dollars, is shared by hundreds of engineers, and needs hours to compile a design. Running them as a pipeline (compile farm, booking, CI, debug data) is a DevOps job.
Interview questions
- Simulation, emulation and FPGA prototyping: when do you use each, and how do you decide where a test runs?
- Design the booking and scheduling system for a shared emulator fleet used by five teams in three time zones.
- An emulation compile takes 9 hours and fails at partitioning twice a week. How do you make the compile flow CI-friendly?
- How do you run firmware and an OS boot before silicon, and how does that work fit into CI?
- A verification engineer wants full waveforms for every failing emulation test. How large is that data, and how do you manage it?
- How does emulation fit into the chip team's CI pipeline, and how do you keep its results trustworthy?
Sign up free to read the full topic
More AI Infrastructure topics
- CUDA Kernel Profiling, Occupancy & the Roofline
- CUDA Memory Hierarchy & Access Patterns
- Disaggregated Prefill-Decode Architecture
- Distributed Training: NCCL, Collectives & Parallelism
- DPUs in GPU Clusters: BlueField & DOCA
- EDA Licenses & Compute Farms
- Firmware CI with Hardware in the Loop
- GPU Architecture & AI Hardware
- GPU Cluster Fabrics: InfiniBand & RoCE
- GPU Driver & Software Stack Release Validation
- GPU Fleet Health: XID Errors, ECC & DCGM
- GPU Node Bring-up & Burn-in
Start free on Cariara · Coding problems · System design studio