The Chip Design Flow as a CI Pipeline
RTL to tape-out as a pipeline: lint, simulation, synthesis, STA, place and route and signoff, which stages run per commit, nightly or weekly, how design data is versioned, and how merges are gated.
Overview
Why this topic
A chip team ships one product every year or two, but its repository changes hundreds of times a day. Every RTL commit can break a block that sits deep inside a flow that takes days to run end to end. The DevOps or infrastructure engineer on a silicon team owns the machinery that turns that flow into a pipeline: what runs on every commit, what runs overnight, what runs once a week, and what must be green before anyone may merge.
The steps are different from software, but the problems are familiar: long jobs, huge artifacts, expensive tools, flaky results, and a release (the tape-out) that cannot be patched after it ships.
Interview questions
- Design the CI pipeline for a chip team of 200 engineers. What runs per commit, nightly and weekly, and why?
- How do you version design data and IP so that any run can be reproduced months later?
- The weekly full-chip run fails timing after 400 commits. How do you find the cause without rerunning the whole flow 400 times?
- What is your merge gate for RTL, and how do you keep it fast as the design grows?
- Explain synthesis and STA to a software engineer, and what the CI system must capture from each run.
- Artifacts from a full-chip flow can reach hundreds of gigabytes. How do you store, share and expire them?
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