Silicon Root of Trust & Key Provisioning in Manufacturing
How a chip proves what it is and what it runs: immutable boot ROM, fuses and OTP, life cycle states, DICE identities, key injection on the tester with HSMs, attestation, key ceremonies and revocation.
Overview
Why this topic
Every security promise a data center makes about its servers (this machine runs only signed firmware, this GPU is genuine, this key never left the chip) bottoms out in a small block of silicon called the hardware root of trust (RoT). The RoT is the first code to run, the holder of the device's secrets and the thing a remote verifier finally trusts.
The infrastructure work around it is mostly not cryptography. It is manufacturing operations: getting a unique secret into each of millions of dies on a tester, recording a certificate for each one, keeping the signing keys in hardware security modules (HSMs) under a quorum, moving each part through its life cycle states, and being able to revoke a key years later without bricking the fleet.
Interview questions
- Design the key provisioning flow for a new accelerator SoC with an integrated root of trust, from wafer test to the first boot in a customer data center.
- Your factory CA runs on an HSM at a contract test house. How do you limit the damage if that site is compromised?
- A firmware signing key may have leaked. What can you do with parts already in the field, and what should the original design have included?
- Explain DICE to an interviewer: why does the device identity depend on the firmware, and how does a verifier use that?
- How do you test a provisioning flow before production, when every mistake burns fuses?
- What is an RMA flow for a part with a root of trust, and why is it dangerous?
Sign up free to read the full topic
More AI Infrastructure topics
- Power & Cooling for GPU Racks
- PyTorch torch.compile, FSDP2 & Training Optimization
- Quantization & Model Compression
- Rack-scale NVLink: Operating GB200/GB300 NVL72
- ROCm & the AMD GPU Stack
- Serving LLMs On-prem: Triton, NIM, vLLM & the Model Store
- Slurm for GPU Clusters
- Speculative Decoding & Parallel Token Generation
- Storage for GPU Training: Parallel Filesystems & GPUDirect Storage
- Tape-out Release Engineering & Signoff Gates
- The Chip Design Flow as a CI Pipeline
- Verification Regressions at Scale
Start free on Cariara · Coding problems · System design studio